Computing systems typically move vast amounts of data and have three types or levels of memory: on-chip or embedded memory in the processor itself (e.g., embedded SRAM or embedded DRAM), main memory (e.g., standalone DRAM), and non-volatile memory (e.g., hard disk drives, magnetic tape, etc.). Dynamic Random Access Memory (DRAM) is essentially used as the main memory of the system. Over the years, the electronics industry has developed DRAM memories that feature reduced bit cell sizes, higher densities, and reduced costs. In order to gain further cost and miniaturization advantages, a great deal of emphasis has been placed on reducing bit cell size to maximize the amount of memory available in a given amount of silicon area. One important parameter associated with semiconductor memories, such as DRAM devices is the feature size of the transistor device that comprises the memory cell. In general, the feature size of the transistor is denoted F, where F corresponds to the minimum gate length that can be produced in the manufacturing process for a circuit. Under present manufacturing systems, the bit-cell area for a one-transistor, one-capacitor DRAM device is typically on the order of 2F by 3F to 4F, which corresponds to a total area of 6 F2 to 8 F2.
DRAM devices have traditionally been made using a simple one-transistor/one-capacitor structure for the basis of each storage cell. Transistor scaling for ever-smaller (higher density) devices presents many challenges. Among others, at small dimensions, various parasitic effects start to appear. Various processing technologies have been developed to overcome these effects, and allow the continuing miniaturization of microelectronic devices. One such technology is Silicon-on-Insulator (SOI) technology, in which a layered silicon-insulator substrate is used in place of conventional silicon substrates. In an SOI device, the active circuit layer is isolated from the substrate. SOI transistors generally have an electrically floating body region. Recent technology has been developed to use this floating-body as an alternative to discrete-trench or stacked-capacitor structures to store information and create a memory bit cell. One such technology is represented by Z-RAM® cells, which consist of a single transistor per bit-cell, with zero capacitors, thus eliminating the deep trench or the complex stacked capacitor. Z-RAM® was developed by, and is a trademark of Innovative Silicon, Inc. of Switzerland. Aspects of the Z-RAM technology, devices, and manufacture are described in the following United States Patent Applications, among others: U.S. application Ser. No. 12/053,398, filed Mar. 21, 2008, and entitled “Manufacturing Process for Zero-Capacitor Random Access Memory Circuits,” and U.S. application Ser. No. 12/019,320, filed Jan. 24, 2008, and entitled “Semiconductor Device with Electrically Floating Body,” each of which is herein incorporated by reference in its entirety.
For SOI structures, the floating body effect is usually an undesirable parasitic element. Embodiments of the present invention are directed to using the parasitic floating body effect advantageously as the basis for various new processing technologies. Such embodiments can be applied to SOI processing technology, as well as any other similar isolated body process technology.
As the channel lengths of DRAM devices become smaller, the densities of the devices increase. In the case of a planar transistor, the channel length of the transistor is reduced as the integration density increases. This, in turn, increases the so-called short-channel effect. In a MOSFET device, a short-channel configuration occurs when the channel length is the same order of magnitude as the depletion-layer widths of the source and drain junctions. Short-channel effects can be attributed to the limitation imposed on electron drift characteristics in the channel, and a modification of the device threshold voltage due to shortened channel length. As channel lengths are excessively decreased in planar devices, the likelihood of a device “punchthrough” effect between the source and a drain of the device is increased, resulting in malfunction of the device. Punchthrough can occur when a high voltage is placed across the transistor from the source to the drain. In this case, an undesirable conductive path is formed through the body region when the transistor should be off. One solution to the punchthrough problem is the use of recessed gate manufacturing techniques in which the transistor is made with a three-dimensional shape having a recessed channel to create a recessed channel (or recessed gate) transistor. The recessed gate effectively creates a long gate length of a device without increasing the feature size of the cell due to the vertical orientation of the device in which the current flows in three-dimensions.
In general, the standard method of creating a recessed gate device is not used in an SOI device. FIG. 1 illustrates a partial array of three separate DRAM cells manufactured from SOI technology, under an embodiment. As shown in FIG. 1, a barrier layer 104 is formed on a semiconductor substrate 102. The barrier layer 104 may be formed of an oxide layer, such as the buried oxide layer (BOX) in an SOI substrate, although it may also be created by other means. A body layer 106 is formed on the barrier layer 104, and may be formed of single crystalline silicon by an epitaxy method or by the SOI substrate fabrication process. In the SOI device shown in FIG. 1, each device is fully isolated from every other device in the array. As shown in FIG. 1, the devices 101, 103 and 105 are separated by isolation layers 108. The isolation layers 108 are formed within body layer 106 and may be formed of an insulating layer, such as a high density plasma oxide layer and/or a silicon oxide layer by chemical vapor deposition, or similar methods. As shown in FIG. 1A, the isolation layers 108 extend to the surface or near the surface of the barrier layer 104. Isolation regions can be provided in two dimensions, however such isolation regions are typically created using lithography methods. That is, they are pre-etched before the gate is formed as done in a standard STI (shallow trench isolation) process. Consequently, the isolation regions are strictly bound by lithography dimension requirements.
In FIG. 1, the gate 110 is separated from the underlying silicon body 106 by a thin gate oxide (not shown) that is also an insulator or insulative layer. This and other layers that may be grown during processing of the device are not shown, but should be understood to be present by those of ordinary skill in the art.
The basic dimension of each cell is defined by the length of the gate 110 of each device. As stated above, this represents the feature size of the transistor (F). For present manufacturing processes, such as illustrated in FIG. 1, the need for substantial isolation between each cell requires that the dimensions of a cell array be a multiple of the individual feature size, F. This is due to the fact that present lithography-based technologies require a minimum printable feature size. This further adds to increased spacing between cells in an array, as well as extra photolithography processing steps.
What is desired, therefore, is a device manufacturing process that creates cell arrays of a minimal dimension and that is not limited by present lithography node rules.
What is further desired is a process that creates a self-aligned lateral isolation for an SOI recessed gate device.
What is yet further desired is a device manufacturing process that efficiently creates an underlap device to reduce the gate induced drain leakage (GIDL) effect.